1. Field of the Disclosure
The disclosure relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching (FFS) mode liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices are driven based on optical anisotropy and polarization characteristics of a liquid crystal material. The LCD devices have been widely used for display units of portable electronic devices, monitors of personal computers, or televisions.
Liquid crystal molecules have a long and thin shape, and the liquid crystal molecules are regularly arranged along in an alignment direction. Light passes through the LCD device along the long and thin shape of the liquid crystal molecules. The alignment of the liquid crystal molecules depends on the intensity or the direction of an electric field applied to the liquid crystal molecules. By controlling the intensity or the direction of the electric field, the alignment of the liquid crystal molecules is controlled to display images.
Generally, an LCD device includes two substrates, which are spaced apart and facing each other, and a liquid crystal layer is interposed between the two substrates. Each of the substrates includes an electrode. The electrodes from respective substrates face one another. An electric field is induced between the electrodes by applying a voltage to each electrode. An alignment direction of liquid crystal molecules changes in accordance with a variation in the intensity or the direction of the electric field.
However, since the LCD device uses a vertical electric field that is perpendicular to the substrates, the LCD device has poor viewing angles.
To resolve the poor viewing angles, an in-plane switching (IPS) mode liquid crystal display (LCD) device has been suggested.
In an IPS mode LCD device, a pixel electrode and a common electrode are alternately disposed on the same substrate, and a horizontal electric field that is parallel to the substrate is induced between the pixel electrode and the common electrode. Liquid crystal molecules are driven by the horizontal electric field and move parallel to the substrate. Accordingly, the IPS mode LCD device has the improved viewing angles.
However, the IPS mode LCD device has disadvantages of low aperture ratio and transmittance. To solve the disadvantages of the IPS mode LCD device, a fringe field switching (FFS) mode LCD device has been suggested.
FIG. 1 is a cross-sectional view of illustrating a pixel region of an array substrate for a related art FFS mode LCD device, FIG. 2 is a cross-sectional view of illustrating a region for a common contact hole of the array substrate of the related art, and FIG. 3 is a cross-sectional view of illustrating a pad area for a data pad electrode of the array substrate of the related art.
In FIG. 1, FIG. 2 and FIG. 3, a gate line (not shown), a gate electrode 5 and a common line 7 are formed on a transparent insulating substrate 1. As not shown in the figures, a gate pad electrode is connected to one end of the gate line.
A gate insulating layer 10 is formed on the gate line, the gate electrode 5, the common line 7, and the gate pad electrode all over the substrate 1.
A semiconductor layer 20 including an active layer 20a and ohmic contact layers 20b is formed over the gate insulating layer 10 corresponding to the gate electrode 5, and source and drain electrodes 33 and 36 spaced apart from each other are formed over the semiconductor layer 20. A data line (not shown) is formed over the gate insulating layer 10. The data line crosses the gate line to define a pixel region P. A data pad electrode 31 is formed in a pad area PA and is connected to one end of the data line. A semiconductor dummy pattern 21 including a first pattern 21a and a second pattern 21b is formed under the data pad electrode 31.
The gate electrode 5, the semiconductor layer 20, the source electrode 33 and the drain electrode 36 constitute a thin film transistor Tr.
A first passivation layer 40 of an inorganic insulating material is formed on the data line, the data pad electrode 31, and the source and drain electrodes 33 and 36. A second passivation layer 50 of an organic insulating material is formed on the first passivation layer 40 and has a flat top surface. The second passivation layer 50 is removed in the pad area PA.
A common contact hole 55 is formed in the first and second passivation layers 40 and 50 and the gate insulating layer 10 and exposes the common line 7.
A common electrode 60 is formed on the second passivation layer 50 and is connected to the common line 7 through the common contact hole 55. The common electrode 60 has a first opening op1 corresponding to a switching area TrA in the pixel region P.
A third passivation layer 63 of an inorganic insulating material is formed on the common electrode 60. Since the second passivation layer 63 is removed in the pad area PA, the third passivation layer 63 is formed directly on the first passivation layer 40 in the pad area PA.
A drain contact hole 68 is formed in the first, second and third passivation layers 40, 50 and 63 and exposes the drain electrode 36 of the thin film transistor Tr.
A pixel electrode 70 of a transparent conductive material is formed on the third passivation layer 63 in the pixel region P and is connected to the drain electrode 36 through the drain contact hole 68. The pixel electrode 70 includes a plurality of second openings op2, which each have a bar shape and are spaced apart from each other.
The array substrate for a related art FFS mod LCD device is manufactured by seven mask processes. A method of manufacturing the array substrate will be briefly explained.
FIGS. 4A to 4C are cross-sectional views of illustrating a pixel region of an array substrate for a related art FFS mode LCD device in steps of manufacturing the same, FIGS. 5A to 5C are cross-sectional views of illustrating a region for a common contact hole of the array substrate in steps of manufacturing the same, and FIGS. 6A to 6C are cross-sectional views of illustrating a pad area for a data pad electrode of the array substrate in steps of manufacturing the same. FIGS. 4A to 4C, FIGS. 5A to 5C, and FIGS. 6A to 6C show steps of forming first and second passivation layers on a substrate.
In FIG. 4A, FIG. 5A and FIG. 6A, a gate line (not shown), a gate pad electrode (not shown), a common line 7 and a gate electrode 5 are formed on a first substrate in a first mask process. A gate insulating layer 10 is formed on the gate line, the gate pad electrode, the common line 7 and the gate electrode 5 all over the substrate 1. A data line (not shown), a data pad electrode 31, source and drain electrodes 33 and 36, and a semiconductor layer 20 are formed over the gate insulating layer 10 in a second mask process. The data line and the data pad electrode 31 are disposed directly on the gate insulating layer 10. The semiconductor layer 20 and the source and drain electrodes 33 and 35 are sequentially on the gate insulating layer 10 corresponding to the gate electrode 5.
Next, a first passivation layer 40 of an inorganic insulating material is formed on the data line, the data pad electrode 31, and the source and drain electrodes 33 and 36 all over the substrate 1.
Then, a second passivation layer 50 of an organic insulating material is formed on the first passivation layer 40 and has a flat top surface. The second passivation layer 50 is patterned in a third mask process, thereby forming a first hole hl1 and a second hole hl2 exposing the first passivation layer 40 corresponding to the drain electrode 36 and the common line 7, respectively, and exposing the first passivation layer 40 in a pad area PA where the data pad electrode 31 is formed and in a gate pad area (not shown) where the gate pad electrode is formed.
If the second passivation layer 50 remains in the gate pad area and the pad area PA, gate and data auxiliary pad electrodes, which are formed later, should be formed too deeply due to the second passivation layer 50, or diameters of pad contact holes exposing the gate and data pad electrodes increase because of a thickness of the second passivation layer 50. In this case, when a printed circuit board is connected to the gate and data auxiliary pad electrodes, conductivity is lowered because conductive balls in an anisotropic conductive film (ACF) used as an adhesive do not break, or stability in electrical connection between the array substrate and the printed circuit board declines because the conductive balls go into the pad contact holes. Thus, to prevent the problems, the second passivation layer 50 is removed in the pad area PA and the gate pad area.
In FIG. 4B, FIG. 5B and FIG. 6B, a photoresist layer (not shown) is formed on the second passivation layer by applying photoresist and is patterned in a fourth mask process, thereby forming a photoresist pattern 81 that exposes the first passivation layer 40 corresponding to the second hole hl2.
Then, a common contact hole 55 exposing the common line 7 is formed by removing the first passivation layer 40 and the gate insulating layer 10 corresponding to the second hole hl2.
Next, in FIG. 4C, FIG. 5C and FIG. 6C, the photoresist pattern 81 of FIG. 4B, FIG. 5B and FIG. 6B on the first passivation layer 40 in the pad area PA and the second passivation layer 50 is removed to there expose the first passivation layer 40 in the pad area PA and the second passivation layer 50.
In the array substrate according to the related art, the second passivation layer 50 is substantially formed through 2 mask processes.
Next, referring to FIG. 1, FIG. 2 and FIG. 3, a common electrode 60 is formed on the second passivation layer 50 in a fifth mask process and is connected to the common line 7 through a common contact hole 55. The common electrode 60 includes a first opening op1.
A third passivation layer 65 is formed on the common electrode 60, and the third passivation layer 65 and the first passivation layer 40 corresponding to the first hole hl1 of FIG. 4C are removed in a sixth mask process to thereby form a drain contact hole 68 exposing the drain electrode 36.
Next, a pixel electrode 70 is formed on the third passivation layer 65 in the pixel region P in a seventh mask process and is connected to the drain electrode 36 through the drain contact hole 68. The pixel electrode 70 includes second openings op2 each having a bar shape and spaced apart from each other.
Therefore, the array substrate of the related art is completed by performing seven mask processes. By the way, since each mask process includes several steps of deposition, light-exposure, development, etch, and so on, the more mask processes are performed, the lower productivity decreases and the more manufacturing costs increase.